View CY7C1021CV33-12ZXCT_3931586.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy7c1021cv33 1-mbit (64k x 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05132 rev. *i revised january 04, 2008 features temperature ranges ? commercial: 0c to 70c ? industrial: ?40c to 85c ? automotive-a: ?40c to 85c ? automotive-e: ?40c to 125c pin and function compatible with cy7c1021bv33 high speed ? t aa = 8 ns (commercial) ? t aa = 10 ns (industrial and automotive-a) ? t aa = 12 ns (automotive-e) cmos for optimum speed and power low active power: 325 mw (max) automatic power down when deselected independent control of upper and lower bits available in pb-free and non pb-free 44-pin 400 mil soj, 44-pin tsop ii and 48-ball fbga packages functional description the cy7c1021cv33 is a high pe rformance cmos static ram organized as 65,536 words by 16 bits. this device has an automatic power down feature th at significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from io pins (io 1 through io 8 ), is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable (bhe ) is low, then data from io pins (io 9 through io 16 ) is written into the location specified on the address pins (a 0 through a 15 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on io 1 to io 8 . if byte high enable (bhe ) is low, then data from memory appears on io 9 to io 16 . for more information, see the ?truth table? on page 9 for a complete description of read and write modes. the input and output pins (io 1 through io 16 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low and we low). for best practice recommendat ions, refer to the cypress application note an1064, sram system guidelines . logic block diagram 64k x 16 ram array io 0 ?io 7 row decoder a 7 a 6 a 5 a 4 a 3 a 0 column decoder a 9 a 10 a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 2 a 1 io 8 ?io 15 ce we ble bhe a 8 [+] feedback [+] feedback
cy7c1021cv33 document number: 38-05132 rev. *i page 2 of 14 selection guide description -8 -10 -12 -15 unit maximum access time 8 10 12 15 ns maximum operating current commercial 95 90 85 80 ma industrial 90 85 ma automotive-a 90 80 ma automotive-e 90 ma maximum cmos standby currentcommercial5555ma industrial 5 5 5 ma automotive-a 5 5 ma automotive-e 10 ma pin configuration figure 1. 44-pin soj/tsop ii [1] figure 2. 48-ball fbga pinout [1] 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 13 a 14 a 8 a 9 a 10 a 11 nc a 12 nc oe bhe ble ce we io 1 io 2 io 3 io 4 io 5 io 6 io 7 io 8 io 9 io 10 io 11 io 12 io 13 io 14 io 15 io 16 v cc v cc v ss v ss nc 10 a 15 we a 11 a 10 a 6 a 0 a 3 ce io 10 io 8 io 9 a 4 a 5 io 11 io 13 io 12 io 14 io 15 v ss a 9 a 8 oe a 7 io 0 bhe nc nc a 2 a 1 ble io 1 io 2 io 3 io 4 io 5 io 6 io 7 a 15 a 14 a 13 a 12 nc nc nc 3 26 5 4 1 d e b a c f g h nc nc v cc v cc v ss note 1. nc pins are not connected on the die. [+] feedback [+] feedback
cy7c1021cv33 document number: 38-05132 rev. *i page 3 of 14 pin definitions pin name soj, tsop pin number bga pin number io type description a 0 ?a 15 1?5, 18?21, 24?27, 42?44 a3, a4, a5, b3, b4, c3, c4, d4, h2, h3, h4, h5, g3, g4, f3, f4 input address inputs. used to select one of the address locations. io 1 ?io 16 [2] 7?10, 13?16, 29?32, 35?38 b6, c6, c5, d5, e5, f5, f6, g6, b1, c1, c2, d2, e2, f2, f1, g1 input or output bidirectional data io lines . used as input or output lines depending on operation. nc 22, 23, 28 a6, d3, e3, e4, g2, h1, h6 no connect no connects . not connected to the die. we 17 g5 input or control write enable input, active low . when selected low, a write is conducted. when deselected high, a read is conducted. ce 6 b5 input or control chip enable input, active low . when low, selects the chip. when high, deselects the chip. bhe , ble 40, 39 b2, a1 input or control byte write select inputs, active low . bhe controls io 16 ? io 9 , ble controls io 8 ? io 1 . oe 41 a2 input or control output enable, active low . controls the direction of the io pins. when low, the io pins are allowed to behave as outputs. when deasserted high, the io pins are tr i-stated and act as input data pins. v ss 12, 34 d1, e6 ground ground for the device . connected to ground of the system. v cc 11, 33 d6, e1 power supply power supply inputs to the device. note 2. io 1 ?io 16 for soj/tsop and io 0 ?io 15 for bga packages. [+] feedback [+] feedback
cy7c1021cv33 document number: 38-05132 rev. *i page 4 of 14 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c ambient temperature with power applied ............................................ ?55 c to +125 c supply voltage on v cc relative to gnd [3] .....?0.5v to +4.6v dc voltage applied to outputs in high z state [3] ...................................... ?0.5v to v cc +0.5v dc input voltage [3] .................................. ?0.5v to v cc +0.5v current into outputs (low)....... .................................. 20 ma static discharge voltage............................................ >2001v (mil-std-883, method 3015) latch up current ..................................................... >200 ma operating range range ambient temperature (t a ) v cc commercial 0 c to +70 c 3.3v 10% industrial ?40 c to +85 c automotive-a ?40 c to +85 c automotive -e ?40 c to +125 c electrical characteristics over the operating range parameter description test conditions -8 -10 -12 -15 unit min max min max min max min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 2.4 2.4 2.4 v v ol output low voltage v cc = min, i ol = 8.0 ma 0.4 0.4 0.4 0.4 v v ih input high voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il input low voltage [3] ?0.3 0.8 ?0.3 0.8 ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc commercial ?1 +1 ?1 +1 ?1 +1 ?1 +1 a industrial ?1 +1 ?1 +1 automotive-a ?1 +1 ?1 +1 automotive-e ?12 +12 i oz output leakage current gnd < v i < v cc , output disabled commercial ?1 +1 ?1 +1 ?1 +1 ?1 +1 a industrial ?1 +1 ?1 +1 automotive-a ?1 +1 ?1 +1 automotive-e ?12 +12 i cc v cc operating supply current v cc = max, i out = 0 ma, f = f max = 1/t rc commercial 95 90 85 80 ma industrial 90 85 automotive-a 90 80 automotive-e 90 i sb1 automatic ce power down current ?ttl inputs max v cc , ce > v ih v in > v ih or v in < v il , f = f max commercial 15 15 15 15 ma industrial 15 15 automotive-a 15 15 automotive-e 20 i sb2 automatic ce power down current ? cmos inputs max v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 commercial 5 5 5 5 ma industrial 5 5 automotive-a 5 5 automotive-e 10 note 3. v il (min) = ?2.0v and v ih (max) = v cc + 0.5v for pulse durations of less than 20 ns. [+] feedback [+] feedback
cy7c1021cv33 document number: 38-05132 rev. *i page 5 of 14 capacitance tested initially and after any design or process changes that may affect these parameters . parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 8 pf c out output capacitance 8pf thermal resistance tested initially and after any design or process changes that may affect these parameters. parameter description test conditions soj tsop ii fbga unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51 65.06 76.92 95.32 c/w jc thermal resistance (junction to case) 34.21 15.86 10.68 c/w ac test loads and waveforms figure 3. ac test loads and waveforms [4] 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 30 pf* * capacitive load consists of all components of the test environment (b) r 317 r2 351 rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z = 50 50 1.5v (c) (a) 3.3v output 5 pf (d) r 317 r2 351 8-ns devices: 10-, 12-, 15-ns devices: high-z characteristics: note 4. ac characteristics (except high-z) for all 8-ns parts are tested using the load conditions shown in figure (a). all other spe eds are tested using the thevenin load shown in figure (b). high-z characteristics are tested for all speeds using the test load shown in figure (d). [+] feedback [+] feedback
cy7c1021cv33 document number: 38-05132 rev. *i page 6 of 14 switching characteristics over the operating range [5] parameter description -8 -10 -12 -15 unit min max min max min max min max read cycle t power [6] v cc (typical) to the first access 100 100 100 100 s t rc read cycle time 8 10 12 15 ns t aa address to data valid 8 10 12 15 ns t oha data hold from address change3333ns t ace ce low to data valid 8 10 12 15 ns t doe oe low to data valid 5567ns t lzoe oe low to low z [7] 0000ns t hzoe oe high to high z [7, 8] 4567ns t lzce ce low to low z [7] 3333ns t hzce ce high to high z [7, 8] 4567ns t pu [9] ce low to power up0000ns t pd [9] ce high to power down 8 10 12 15 ns t dbe byte enable to data valid 5567ns t lzbe byte enable to low z0000ns t hzbe byte disable to high z 4567ns write cycle [10] t wc write cycle time 8 10 12 15 ns t sce ce low to write end 7 8 9 10 ns t aw address setup to write end 7 8 9 10 ns t ha address hold from write end0000ns t sa address setup to write start0000ns t pwe we pulse width 6 7 8 10 ns t sd data setup to write end5568ns t hd data hold from write end0000ns t lzwe we high to low z [7] 3333ns t hzwe we low to high z [7, 8] 4567ns t bw byte enable to end of write6789ns notes 5. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, and input pulse levels of 0 t o 3.0v. 6. t power gives the minimum amount of time that the power supply is at typical v cc values until the first memory access is performed. 7. at any temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 8. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (d) of ?ac test loads and waveforms? on page 5. transition is measured 500 mv from steady state voltage. 9. this parameter is guaranteed by design and is not tested. 10. the internal write time of the memory is defined by the overlap of ce low, we low, and bhe /ble low. ce , we, and bhe /ble is low to initiate a write. the transition of these signals terminate the write. the input data setup and hold timing is referenced to the leading edge of the signal that terminates the write. [+] feedback [+] feedback
cy7c1021cv33 document number: 38-05132 rev. *i page 7 of 14 switching waveforms figure 4. read cycle no. 1 (address transition controlled) [11, 12] figure 5. read cycle no. 2 (oe controlled) [12, 13] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd t dbe t lzbe t hzce high impedance i cc i sb oe ce address data out v cc supply bhe ,ble current notes 11. device is continuously selected. oe , ce , bhe, and/or ble = v il . 12. we is high for read cycle. 13. address valid prior to or coincident with ce transition low. [+] feedback [+] feedback
cy7c1021cv33 document number: 38-05132 rev. *i page 8 of 14 figure 6. write cycle no. 1 (ce controlled) [14, 15] figure 7. write cycle no. 2 (ble or bhe controlled) switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw t data io address ce we bhe ,ble t hd t sd t bw t sa t ha t aw t pwe t wc t sce data io address bhe ,ble ce we notes 14. data io is high impedance if oe, bhe, and/or ble = v ih . 15. if ce goes high simultaneously with we going high, the output remains in a high impedance state. [+] feedback [+] feedback
cy7c1021cv33 document number: 38-05132 rev. *i page 9 of 14 figure 8. write cycle no. 3 (we controlled, low) truth table ce oe we ble bhe io 1 ? io 8 io 9 ? io 16 mode power hxxxxhigh zhigh zpower down standby (i sb ) l l h l l data out data out read ? all bits active (i cc ) l h data out high z read ? lower bits only active (i cc ) h l high z data out read ? upper bits only active (i cc ) l x l l l data in data in write ? all bits active (i cc ) l h data in high z write ? lower bits only active (i cc ) h l high z data in write ? upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) l x x h h high z high z selected, outputs disabled active (i cc ) switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw t sa t lzwe t hzwe data io address ce we bhe ,ble [+] feedback [+] feedback
cy7c1021cv33 document number: 38-05132 rev. *i page 10 of 14 ordering information speed (ns) ordering code package diagram package type operating range 8 cy7c1021cv33-8baxc 51-85096 48-ball fbga (pb-free) commercial 10 cy7c1021cv33-10vxc 51-85082 44-pin (400-mil) molded soj (pb-free) commercial cy7c1021cv33-10zxc 51-85087 44-pin tsop type ii (pb-free) cy7c1021cv33-10baxi 51-85096 48- ball fbga (pb-free) industrial cy7c1021cv33-10zsxa 51-85087 44-pin tsop type ii (pb-free) automotive-a 12 cy7c1021cv33-12zxc 51-85087 44-pin tsop type ii (pb-free) commercial cy7c1021cv33-12bai 51-85096 48-ball fbga industrial cy7c1021cv33-12vxe 51-85082 44-pin (400-mil) molded soj (pb-free) automotive-e cy7c1021cv33-12zsxe 51-85087 44-pin tsop type ii (pb-free) 15 cy7c1021cv33-15zxc 51-85087 44-pin tsop type ii (pb-free) commercial cy7c1021cv33-15zsxa 51-85087 44-pin tsop type ii (pb-free) automotive-a the 44 pin tsop ii package containing the automotive grade device is designated as ?zs?, while t he same package containing the commercial/industrial grade device is ?z?. [+] feedback [+] feedback
cy7c1021cv33 document number: 38-05132 rev. *i page 11 of 14 package diagrams figure 9. 44-pin (400 mil) molded soj 51-85082-*b [+] feedback [+] feedback
cy7c1021cv33 document number: 38-05132 rev. *i page 12 of 14 figure 10. 44-pin thin small outline package type ii package diagrams (continued) 51-85087-*a [+] feedback [+] feedback
cy7c1021cv33 document number: 38-05132 rev. *i page 13 of 14 figure 11. 48-ball fbga (7 x 7 x 1.2 mm) package diagrams (continued) g f e d c b a 5 64321 pin 1 corner 5.25 3.75 0.75 0.75 ?0.300.05(48x) ?0.25mcab 0.15(4x) 0.210.05 1.20 max. seating plane 0.530.05 0.25 c 0.10 c h e h f g a b c d 6 5 12 3 4 pin 1 corner top view bottom view 7.000.10 7.000.10 a b ?0.05 m c (laser mark) b a c 7.000.10 7.000.10 1.875 2.625 0.36 518506g [+] feedback [+] feedback
document number: 38-05132 rev. *i revised january 04, 2008 page 14 of 14 all product and company names mentioned in this document are the trademarks of their respective holders. cy7c1021cv33 ? cypress semiconductor corporation, 2001-2008. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reas onably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: cy7c1021cv33, 1-mbit (64k x 16) static ram document number: 38-05132 rev. ecn no. issue date orig. of change description of change ** 109472 12/06/01 hgk new datasheet *a 115044 05/08/02 hgk ram7 version c4k x 16 async removed ?preliminary? *b 115808 06/25/02 hgk i sb1 and i cc values changed *c 120413 10/31/02 dfp updated bga pin e4 to nc *d 238454 see ecn rkf 1) added automotive specifications to datasheet 2) added pb-free devices in the ordering information *e 334398 see ecn syt added pb-free on page 9 and 10 *f 493565 see ecn nxr added automotive-a operating range corrected typo in the pin definition table changed the description of i ix from input load current to input leakage current in dc electrical characteristics table removed i os parameter from dc electrical characteristics table updated the ordering information table *g 563963 see ecn vkn added t power specification in the ac switching characteristics table added footnote 8 *h 1390863 see ecn vkn/aesa corrected tsop ii package outline *i 1891366 see ecn vkn/aesa added -10zsxa part in the ordering information table updated ordering information table [+] feedback [+] feedback

▲Up To Search▲

Price & Availability of CY7C1021CV33-12ZXCT

	To Download CY7C1021CV33-12ZXCT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .